View LT1786F_75896.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT1786F SMBus Programmable CCFL Switching Regulator
FEATURES
s s s s
s s s
Wide Battery Input Range: 4.5V to 30V Grounded Lamp or Floating Lamp Configurations Open Lamp Protection Precision 100A Full-Scale DAC Programming Current 2-Wire SMBus Interface Two Selectable SMBus Addresses DAC Setting Is Retained in Shutdown
to-lamp-current control" and communicates using the 2-wire SMBus serial interface. The LT1786F acts as an SMBus slave device using one of two selectable SMBus addresses set by the address pin ADR. On Power-up, the DAC output current assumes midrange or zero scale, depending on the logic state of the ADR pin.The entire IC can be shut down through the SMBSUS pin or by setting the SHDN bit = 1 in the SMBus command byte. Digital data for the DAC output current is retained internally and the supply current drops to 40A for standby operation. The active low SHDN pin disables the CCFL control circuitry, but keeps the DAC alive. Supply current in this operating mode drops to 150A. The LT1786F control circuitry operates from a logic supply voltage of 3.3V or 5V. The IC also has a battery supply pin that operates from 4.5V to 30V. The LT1786F draws 6mA typical quiescent current. A 200kHz switching frequency minimizes magnetic component size. Current mode switching techniques with cycle-by-cycle limiting gives high reliability and simple loop frequency compensation. The LT1786F is available in a 16-pin narrow SO package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIONS
s s s
Notebook and Palmtop Computers Portable Instruments Personal Digital Assistants
DESCRIPTION
The LT (R)1786F is a fixed frequency, current mode, switching regulator that provides the control function for Cold Cathode Fluorescent Lighting (CCFL). The IC includes an efficient high current switch, an oscillator, output drive logic, control circuitry and a micropower 6-bit 100A fullscale current output DAC. The DAC provides simple "bits-
TYPICAL APPLICATION
90% Efficient Floating CCFL with 2-Wire SMBus Control of Lamp Current
D1 BAT85 CCFL BACKLIGHT APPLICATION CIRCUITS CONTAINED IN THIS DATA SHEET ARE COVERED BY U.S. PATENT NUMBER 5408162 AND OTHER PATENTS PENDING 1 2 3 C7, 1F 4 5 SHUTDOWN 6 7 8 CCFL PGND ICCFL DIO CCFL VSW BULB 16 15 R2 220k C5 1000pF 3 2 1 C3B 2.2F 35V R1 750 4 5 LAMP 10 6 L1 = COILTRONICS CTX210605 C2 27pF 3kV L1 L2 = COILTRONICS CTX100-4 *DO NOT SUBSTITUTE COMPONENTS COILTRONICS (561) 241-7876 BAT 8V TO 28V
14 BAT LT1786F 13 CCFL VC ROYER AGND SHDN SMBSUS ADR VCC IOUT SCL SDA 12 11 10 9 TO SMBus HOST
ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3A AND C3B. MAKE 3CB ESR 0.5 TO PREVENT DAMAGE TO THE LT1786F HIGH-SIDE SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKI OR MKP-20 = PANASONIC ECH-U Q1, Q2 = ZETEX ZTX849 OR ROHM 2SC5001
U
U
U
+
+
C3A 2.2F 35V
+
C4 2.2F
3V VCC 6.5V
C1* 0.068F R3 100k Q2* Q1*
L2 100H
D1 1N5818
1786F TA01
0A TO 50A ICCFL CURRENT GIVES 0mA TO 6mA LAMP CURRENT FOR A TYPICAL DISPLAY.
FOR ADDITIONAL CCFL/LCD CONTRAST APPLICATION CIRCUITS, REFER TO THE LT1182/83/84/84F DATA SHEET
1
LT1786F
ABSOLUTE MAXIMUM RATINGS
VCC ........................................................................... 7V BAT, Royer, BULB .................................................. 30V CCFL VSW ............................................................... 60V Shutdown ................................................................. 6V ICCFL Input Current .............................................. 10mA DIO Input Current (Peak, < 100ms).................... 100mA Digital Inputs .............................. - 0.3V to (VCC + 0.3V) Digital Outputs ............................ - 0.3V to (VCC + 0.3V) DAC Output Voltage ..................... - 15V to (VCC + 0.3V) Junction Temperature (Note 1) ............................ 100C Operating Ambient Temperature Range ..... 0C to 70C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW CCFL PGND 1 ICCFL 2 DIO 3 CCFL VC 4 AGND 5 SHDN 6 SMBSUS 7 ADR 8 16 CCFL VSW 15 BULB 14 BAT 13 ROYER 12 VCC 11 IOUT 10 SCL 9 SDA
ORDER PART NUMBER LT1786FCS
S PACKAGE 16-LEAD PLASTIC SO
TJMAX = 100C, JA = 100C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25C, VCC = SHUTDOWN = SMBSUS = SCL = SDA = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DIO = IOUT = GND, CCFL VC = 0.5V, unless otherwise specified.
SYMBOL IQ ISUS ISHDN PARAMETER Supply Current SMBSUS Supply Current SHUTDOWN Supply Current SHUTDOWN Input Bias Current SHUTDOWN Threshold Voltage f DC(MAX) BV Switching Frequency Maximum Switch Duty Cycle Switch Breakdown Voltage Switch Leakage Current ICCFL Summing Voltage ICCFL Summing Voltage for Input Programming Current CCFL VC Offset Sink Current CCFL VC Source Current for ICCFL Programming Current CCFL VC to DIO Current Servo Ratio CCFL VC Low Clamp Voltage CCFL VC High Clamp Voltage CCFL VC Switching Threshold CCFL High-Side Sense Servo Current Measured at CCFL VSW, ISW = 50mA, ICCFL = 100A, CCFL VC = Open Measured at CCFL VSW
q
CONDITIONS 3V VCC 6.5V, IOUT = 0A SMBSUS = 0V or Command Code Bit 7 = 1, CCFL VC = Open (Note 2) SHUTDOWN = 0V, CCFL VC = Open (Note 2) SHUTDOWN = 0V, CCFL VC = Open
q q q q q
MIN
TYP 6 40 150 5
MAX 9.5 100 300 10 1.2 225 240
UNITS mA A A A V kHz kHz % % V
0.45 175 160 80 75 60
0.85 200 200 85 85 70
Measured at CCFL VSW VSW = 12V, Measured at CCFL VSW VSW = 30V, Measured at CCFL VSW 3V VCC 6.5V
q
20 40 0.425 0.385 0.465 0.465 5 -5
q q q q q q
0.505 0.555 15 15 5.20 104 0.3 2.4 1.3 1.07
ICCFL = 0A to 100A CCFL VC = 1.5V, Positive Current Measured into Pin ICCFL = 25A, 50A, 75A, 100A, CCFL VC = 1.5V DIO = 5mA out of Pin, Measure I(VC) at CCFL VC = 1.5V VBAT - VBULB = BULB Protect Servo Voltage ICCFL = 100A CCFL VSW DC = 0% ICCFL = 100A, I(VC) = 0A at CCFL VC = 1.5V
5 4.95 99 0.1 2.1 0.95 1.00
4.70 94 1.7 0.6 0.93
A/A A/mA V V V A
2
U
W
U
U
WW
W
A A V V mV A
LT1786F
ELECTRICAL CHARACTERISTICS
TA = 25C, VCC = SHUTDOWN = SMBSUS = SCL = SDA = 3.3V, BAT = Royer = BULB = 12V, I CCFL = CCFL VSW = Open, DIO = IOUT = GND, CCFL VC = 0.5V, unless otherwise specified.
SYMBOL PARAMETER CCFL High-Side Sense Servo Current Line Regulation BULB Protect Servo Voltage BULB Input Bias Current ILIM VSAT IQ ISW CCFL Switch Current Limit CCFL Switch On Resistance Supply Current Increase During CCFL Switch On Time DAC Resolution DAC Full-Scale Current DAC Zero Scale Current DAC Differential Nonlinearity DAC Supply Voltage Rejection IIN VIH Logic Input Current High Level Input Voltage 3V VCC 6.5V, IOUT = Full Scale, V(IOUT) = 0.465V 0V VIN VCC ADR SMBSUS SCL, SDA SMBSUS, ADR SCL, SDA IOUT = 3mA, SDA Only IOUT = 1.6mA, SMBSUS = 0V, Measured at SHDN Pin V(IOUT) = 0.465V
q
CONDITIONS BAT = 5V to 30V, ICCFL = 100A, I(VC) = 0A at CCFL VC = 1.5V
q q
MIN
TYP 0.1
MAX 0.16 150 7.5 9 3.0 2.6 1.0 30
UNIT %/V A V A A A mA/A Bits
CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins ICCFL = 100A, I(VC) = 0A at CCFL VC = 1.5V, Servo Voltage Measured between BAT and BULB Pins ICCFL = 100A, I(VC) = 0A at CCFL VC = 1.5V Duty Cycle = 50% Duty Cycle = 75% (Note 3) CCFL ISW = 1A CCFL ISW = 1A
50 6.5
100 7.0 5
q q q
1.25 0.9
1.9 1.6 0.6 20 6
98 96
100 100 0.1 0.2
102 104 200 1 2 1
A A nA LSB LSB A V V V
V(IOUT) = 0.465V
q q q q q q q q q q q
VCC - 0.3 2.4 1.4 0.8 0.6 0.4 0.4 10 4.7 4.0 4.7 4.0 300 250 4.7 4.0 50 300 1000 100
VIL VOL
Low Level Input Voltage Low Level Output Voltage
V V V V kHz s s s s ns ns s s ns ns
SMBus Timing (Notes 4, 5) fSMB tBUF tHD:STA tSU:STA tSU:STO tHD:DAT tSU:DAT tLOW tHIGH tf tr SMB Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall Time Clock/Data Rise Time
q q q q q q q q q q q
The q denotes specifications which apply over the specified operating temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LT1786FCS: TJ = TA + (PD)(100C/W) Note 2: Does not include switch leakage.
Note 3: For duty cycles (DC) between 50% and 80%, minimum guaranteed switch current is given by ILIM = 1.4(1.393 - DC) for the LT1786F due to internal slope compensation circuitry. Note 4: Timings for all signals are referenced to VIH and VIL signals. Note 5: These parameters are guaranteed by design and are not tested in production. Refer to the Timing Diagrams for additional information.
3
LT1786F TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature
10 9 8 100 90 8O 70
ISUS (A)
SHDN SUPPLY CURRENT (A)
SUPPLY CURRENT (mA)
7 6 5 4 3 2 1 0 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G01
SHDN Input Bias Current vs Temperature
6 1.2
SHDN INPUT BIAS CURRENT (A)
SHDN THRESHOLD VOLTAGE (V)
5 4 3 2 1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G04
1.0 0.9 0.8 0.7 0.6 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G05
CCFL FREQUENCY (kHz)
VCC = 5V VCC = 3V
Maximum Duty Cycle vs Temperature
95 93
CCFL MAXIMUM DUTY CYCLE (%)
ICCFL SUMMING VOLTAGE (V)
91 89 87 85 83 81 79 77 75 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G07
ICCFL SUMMING VOLTAGE (mV)
4
UW
ISUS Current vs Temperature
300 SMBSUS = 0V 270 240 210 180 150 120 90 60 30 -5 25 50 75 100 125 150 TEMPERATURE (C)
1786 G02
SHDN Supply Current vs Temperature
SHDN = 0V
60 50 40 30 20 10 0 -55 -25 VCC = 5V VCC = 3V
VCC = 5V VCC = 3V
0 -55 -25
-5
25 50 75 100 125 150 TEMPERATURE (C)
1786 G03
SHDN Threshold Voltage vs Temperature
240 230 220 210 200 190 180 170
Frequency vs Temperature
1.1
160 -75 -50 -25
0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G06
ICCFL Summing Voltage vs Temperature
0.53 0.52 0.51 0.50 0.49 0.48 0.47 0.46 0.45 0.44 0.43 0.42 0.41 0.40 0.39 0.38 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G08
ICCFL Summing Voltage Load Regulation
5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0
T = -55C
T = 25C
T = 125C
20 40 60 80 100 120 140 160 180 200 ICCFL PROGRAMMING CURRENT (A)
1786 G09
LT1786F TYPICAL PERFORMANCE CHARACTERISTICS
VC Sink Offset Current vs Temperature
10
CCFL VC SINK OFFSET CURRENT (A)
POSITIVE DIO VOLTAGE (V)
9 8 7 6 5 4
CCFL VC = 1.5V
CCFL VC SOURCE CURRENT FOR ICCFL PROGRAMMING CURRENT (A/A)
CCFL VC = 1.0V
3 2 1 CCFL VC = 0.5V 0 -1 -2 -3 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G10
Negative DIO Voltage vs Temperature
CCFL VC DIO CURRENT SERVO RATIO (A/mA)
1.6 1.4
103 102 101 100 99 98 97 96
CCFL VC LOW CLAMP VOLTAGE (V)
NEGATIVE DIO VOLTAGE (V)
I(DIO) = 10mA 1.2 1.0 0.8 0.6 0.4 0.2 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G13
I(DIO) = 5mA I(DIO) = 1mA
VC High Clamp Voltage vs Temperature
CCFL VC SWITCHING THRESHOLD VOLTAGE (V)
2.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7
CCFL VC HIGH CLAMP VOLTAGE (V)
2.3 2.2 2.1 2.0 1.9 1.8 1.7 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G16
BULB PROTECT SERVO VOLTAGE (V)
UW
CCFL VC Source Current for ICCFL Programming Current vs Temperature
5.10 5.05 5.00 4.95 4.90 4.85 4.80 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G11
Positive DIO Voltage vs Temperature
1.2 1.0 I(DIO) = 10mA 0.8 0.6 0.4 0.2 0 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G12
ICCFL = 100A ICCFL = 50A ICCFL = 10A
I(DIO) = 5mA
I(DIO) = 1mA
VC to DIO Current Servo Ratio vs Temperature
0.30 0.25 0.20 0.15 0.10 0.05
VC Low Clamp Voltage vs Temperature
I(DIO) = 10mA I(DIO) = 1mA I(DIO) = 5mA
95 -75 - 50 -25
0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G14
0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G15
VC Switching Threshold vs Temperature
7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6
BULB Protect Servo Voltage vs Temperature
ICCFL = 100A
ICCFL = 50A
ICCFL = 10A
0.6 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G17
6.5 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G18
5
LT1786F TYPICAL PERFORMANCE CHARACTERISTICS
BULB Input Bias Current vs Temperature
CCFL HIGH-SIDE SENSE SUPPLY CURRENT (A) 10 BULB INPUT BIAS CURRENT (A) 150 140 130 120 110 100 90 80 70 60 50 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G20
CCFL HIGH-SIDE SENSE NULL CURRENT (A)
8
6
4
2
0 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1787 G19
High-Side Sense Null Current Line Regulation vs Temperature
CCFL HIGH-SIDE SENSE LINE REGULATI0N (%V)
0.160 0.140 0.120 0.100 0.080 0.060 0.040 0.020 0.000 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G22
CCFL VSW SAT VOLTAGE (V)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.3 0.9 1.2 0.6 SWITCH CURRENT (A) 1.5
1787 G23
CCFL VSW CURRENT LIMIT (A)
Forced Beta vs ISW on VSW
110
FULL-SCALE OUTPUT CURRENT (A)
100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 CCFL ISW (A)
1786 G25
FORCED BETA
6
UW
High-Side Sense Supply Current vs Temperature
1.060 1.040 1.020 1.000 0.980 0.960
High-Side Sense Null Current vs Temperature
0.940 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G21
VSW Sat Voltage vs Switch Current
1.0 0.9
2.0 2.5
VSW Current Limit vs Duty Cycle
T = 25C T = 125C T = -5C
T = 0C T = 25C 1.5 T = 125C MINIMUM
1.0
0.5
0 0 10 20 30 40 50 60 DUTY CYCLE (%) 70 80 90
1786 G24
Full-Scale Output Current vs Temperature
104 V(IOUT) = 0.465V 103 102 101 100 99 98 97 96 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
1786 G26
LT1786F TYPICAL PERFORMANCE CHARACTERISTICS
DNL vs Code
1.0 0.8 0.6 0.4
1.0 0.8 0.6 0.4
DNL (LSB)
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16 32 CODE 48 64
1786 G27
INL (LSB)
0.2
PIN FUNCTIONS
CCFL PGND (Pin 1): This pin is the emitter of an internal NPN power switch. CCFL switch current flows through this pin and permits internal, switch-current sensing. The regulator provides a separate analog ground and power ground to isolate high current ground paths from low current signal paths. Linear Technology recommends the use of star-ground layout techniques. ICCFL (Pin 2): This pin is the input to the CCFL lamp current programming circuit. This pin internally regulates to 465mV. The pin accepts a DC input current signal of 0A to 100A full scale from the DAC. This input signal is converted to a 0A to 500A source current at the CCFL VC pin. As input programming current increases, the regulated lamp current increases. DIO (Pin 3): This pin is the common connection between the cathode and anode of two internal diodes. The remaining terminals of the two diodes connect to ground. In a grounded-lamp configuration, DIO connects to the low voltage side of the lamp. Bidirectional lamp current flows in the DIO pin and thus the diodes conduct alternately on half cycles. Lamp current is controlled by monitoring onehalf of the average lamp current. The diode conducting on negative half cycles has one-tenth of its current diverted to the CCFL VC pin. This current nulls against the source current provided by the lamp-current programmer circuit. A single capacitor on the CCFL VC pin provides both stable loop compensation and an averaging function to the halfwave-rectified sinusoidal lamp current. Therefore, input programming current relates to one-half of average lamp current. This scheme reduces the number of loop compensation components and permits faster loop transient response in comparison to previously published circuits. If a floating lamp configuration is used, ground the DIO pin. CCFL VC (Pin 4): This pin is the output of the lamp current programmer circuit and the input of the current comparator for the CCFL regulator. Its uses include frequency compensation, lamp-current averaging for grounded-lamp circuits and current limiting. The voltage on the CCFL VC pin determines the current trip level for switch turn-off. During normal operation this pin sits at a voltage between 0.95V (zero switch current) and 2.1V (maximum switch current) with respect to analog ground (AGND). This pin has a high impedance output and permits external voltage clamping to adjust current limit. A single capacitor to ground provides stable loop compensation. This simplified loop compensation method permits the CCFL regulator to exhibit single-pole transient response behavior and virtually eliminates transformer output overshoot.
UW
INL vs Code
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16 32 CODE 48 64
1786 G28
U
U
U
7
LT1786F
PIN FUNCTIONS
AGND (Pin 5): This is the low current analog ground. It is the negative sense terminal for the internal 1.24V reference and the ICCFL summing voltage in the LT1786F. Connect low current signal paths that terminate to ground and frequency compensation components that terminate to ground directly to this pin for best regulation and performance. SHDN (Pin 6): Pulling this pin low causes regulator shutdown with quiescent current typically reduced to 150A. In this condition, the DAC circuitry remains alive and the DAC IOUT level is maintained. If this pin is not used, use a pull-up resistor to force a logic high level (maximum of 6V). The pin can be floated and an internal current source will pull the pin to a logic high level. However, poor PCB layout techniques can permit switching noise to inject into this pin and cause erratic operation. LTC recommends the use of a pull-up resistor. If the SMBSUS pin is pulled low or Bit 7 = 1 in the Command Byte, complete IC shutdown is enabled. An internal open drain N-channel device turns on and pulls the SHDN pin low. The N-channel can sink up to 1.6mA. SMBSUS (Pin 7): Pulling this pin low causes complete shutdown for the IC with quiescent current typically reduced to 40A. In this SMBus suspend condition, the DAC retains its last output current setting and returns to this level when the logic low signal at this pin is removed. If this pin is not used, use a pull-up resistor to force a logic high level or tie it directly to VCC. Poor PCB layout techniques can permit switching noise to inject into this pin and cause erratic operation. A small value capacitor may be required to filter out this noise. Setting Bit 7 = 1 in the Command Byte also enables an SMBus suspend condition. Enabling an SMBus suspend condition turns on an internal open drain N-channel device which pulls the SHDN pin low. The N-channel device sinks up to 1.6mA at the SHDN pin. ADR (Pin 8): This is the SMBus address select pin. Tie this pin to either VCC or GND to select one of two SMBus addresses to which the LT1786F will respond. If the ADR pin is tied to GND, the SMBus address is set to 58 (HEX) and the DAC IOUT powers up to zero scale. If the ADR pin is tied to VCC, the SMBus address is set to 5A (HEX) and the DAC IOUT powers up to half scale. If a different value is required for the DAC IOUT on power-up, use the SHDN pin to keep the CCFL regulator off until the required value has been programmed for the DAC via the SMBus. SDA (Pin 9): This is the SMBus bidirectional data input and digital output pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. SDA is a high impedance pin while data is shifted into the pin and an open-drain N-channel output during acknowledges. SDA requires a pull-up resistor or current source to VCC. SCL (Pin 10): This is the SMBus clock input pin. Data is shifted into the SDA pin at the rising edges of the SCL clock during data transfer. SCL is a high impedance pin. SCL requires a pull-up resistor or current source to VCC. IOUT (Pin 11): This pin is the current output for the DAC and provides a full-scale output current of 100A 4A over temperature. Initial accuracy is 100A 2A.The pin can be biased from - 10V to (VCC - 1.3V). This pin is typically tied directly to the ICCFL pin and provides the programming current which sets the operating lamp current. The IOUT pin has very little bias voltage change when tied to the ICCFL pin as ICCFL is regulated. The programming current is sourced from the IOUT pin and sunk by the ICCFL pin. VCC (Pin 12): This is the supply pin for the LT1786F. The IC accepts an input voltage range of 3V minimum to 6.5V maximum with little change in quiescent current (zero switch current). An internal, low-dropout regulator provides a 2.4V supply for most of the internal circuitry. Supply current increases as switch current increases at a rate approximately 1/50 of switch current. This corresponds to a forced Beta of 50 for the power switch. The IC incorporates undervoltage lockout by sensing regulator dropout and locking out switching for input voltages below 2.5V. Hysteresis is not used to maximize the range of input voltage. The typical input voltage is a 3.3V or 5V logic supply.
8
U
U
U
LT1786F
PIN FUNCTIONS
ROYER (Pin 13): This pin connects to the center-tapped primary of the Royer converter and is used with the BAT pin in a floating-lamp configuration where lamp current is controlled by sensing Royer primary-side converter current. This pin is the inverting terminal of a high-side current sense amplifier. The typical quiescent current is 50A into the pin. If the CCFL regulator is not used in a floating-lamp configuration, tie the Royer and BAT pins together. BAT (Pin 14): This pin connects to the battery or AC wall adapter voltage from which the CCFL Royer converter operates. This voltage is typically higher than the VCC supply voltage but can equal VCC if VCC is a 5V logic supply. The BAT voltage must be at least 2.1V greater than the internal 2.4V regulator or 4.5V. This pin provides biasing for the lamp-current programming block, is used with the Royer pin for floating-lamp configurations and connects to one input for the open-lamp protection circuitry. For floating-lamp configurations, this pin is the noninverting terminal of a high-side current sense amplifier. The typical quiescent current is 50A into the pin. The BAT and Royer pins monitor the primary-side Royer converter current through an internal 0.1 topside current sense resistor. A 0A to 1A primary-side, center tap converter current is translated to an input signal range of 0mV to 100mV for the current sense amplifier. This input range translates to a 0A to 500A sink current at the CCFL VC pin that nulls against the source current provided by the programmer circuit. The BAT pin also connects to the topside of the internal clamp between the BAT and BULB pins that is used for open-lamp protection. BULB (Pin 15): This pin connects to the low side of a 7V threshold comparator between the BAT and BULB pins. This circuit sets the maximum voltage level across the primary side of the Royer converter under all operating conditions and limits the maximum secondary output under start-up conditions or open-lamp conditions. This eases transformer voltage rating requirements. Set the voltage limit to ensure lamp start-up with worst-case, lamp start voltages and cold temperature, system operating conditions. The BULB pin connects to the junction of an external divider network. The divider network connects from the center tap of the Royer transformer or the actual battery supply voltage to the topside of the current source "tail inductor." A capacitor across the top of the divider network filters switching ripple and sets a time constant that determines how quickly the clamp activates. When the comparator activates, sink current is generated to pull the CCFL VC pin down. This action transfers the entire regulator loop from current mode operation into voltage mode operation. CCFL VSW (Pin 16): This pin is the collector of the internal NPN power switch for the CCFL regulator. The power switch provides a minimum of 1.25A. Maximum switch current is a function of duty cycle as internal slope compensation ensures stability with duty cycles greater than 50%. Using a driver loop to automatically adapt base drive current to the minimum required to keep the switch in a quasi-saturation state yields fast switching times and high efficiency operation. The ratio of switch current to driver current is about 50:1.
U
U
U
9
LT1786F
BLOCK DIAGRAM
SHDN 6
SHUTDOWN
0A TO 100A FROM IOUT
2 ICCFL
SCL 10 SDA 9
SMBus INTERFACE
ADR
10
W
LT1786F SMBus Programmable CCFL Switching Regulator
VCC 12 BAT 14 ROYER 13 2.4V REGULATOR UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CCFL VSW 16 200kHz OSC R4 0.1 LOGIC DRIVE Q1
-
D2 6V R3 1k Q5 1x Q3 2x Q4 5x Q7 9x Q8 1x Q9 3x D1 Q6 2x Q11 gm
+
COMP
ANTISAT
+
CURRENT AMP R1 0.125
-
GAIN = 4.4
+
CCFL
-
V1 0.465V
Q10 2x
5 AGND
3 DIO
15 BULB
4 CCFL VC
1 CCFL PGND
SMBSUS SD POWER-ON RESET 7
SHUTDOWN 1 REGISTER A 3-BIT LATCH EN1
SD VOLTAGE REFERENCE RADJ
1
REGISTER B 1-BIT LATCH EN2 SD
SD 6 8 REGISTER C 6-BIT LATCH EN2 6 6-BIT CURRENT DAC 11 IOUT
1786 BD
LT1786F TI I G DIAGRA S
Timing for SMBus Interface
t BUF SDA
SCL t LOW STOP START t HIGH t HD:DAT t SU:STA t SU:DAT START t SU:STO
1786 TD01
ADR GND SMBUS ADDRESS COMMAND BYTE DATA BYTE
SHDN
ACK
ACK
SDA
0
1
0
1
1
0
1
X
X
X
X
X
X
X
1
1
1
1
1
1
X
X
ACK
WR
SCL
S 1 2
3
4
5
6
IOUT S = START P = STOP * = OPTIONAL
1786 TD02
APPLICATIONS INFORMATION
Introduction Current generation portable computers and instruments use backlit Liquid Crystal Displays (LCDs). Cold Cathode Fluorescent Lamps (CCFLs) provide the highest available efficiency in back lighting the display. Providing the most light out for the least amount of input power is the most important goal. These lamps require high voltage AC to operate, mandating an efficient high voltage DC/AC converter. The lamps operate from DC, but migration effects damage the lamp and shorten its lifetime. Lamp drive should contain zero DC component. In addition to good efficiency, the converter should deliver the lamp drive in the form of a sine wave. This minimizes EMI and RF emissions. Such emissions can interfere with other devices and can also degrade overall operating efficiency. Sinusoidal CCFL drive maximizes current-to-light conversion in the lamp. The circuit should also permit lamp intensity control from zero to full brightness with no hysteresis or "pop-on." The small size and battery-powered operation associated with LCD equipped apparatus dictate low component count and high efficiency for these circuits. Size constraints place severe limitations on circuit architecture and long battery life is a priority. Laptop and handheld portable computers offer an excellent example. The CCFL and its power supply can be responsible for almost 50% of the
U
W
W
U
U
UW
t HD:STA tr tf
t HD:STA
STOP
Operating Sequence SMBus Write Byte Protocol, with SMBus Address = 0101101B, Command Byte = 0XXXXXXXB and Data Byte = 111111XXB
VCC
7
8
9
* P 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FULL-SCALE CURRENT ZERO-SCALE CURRENT
11
LT1786F
APPLICATIONS INFORMATION
battery drain. Additionally, all components, including PC board and hardware, usually must fit within the LCD enclosure with a height restriction of 5mm to 10mm. The CCFL regulator drives an inductor that acts as a switched-mode current source for a current-driven Royerclass converter with efficiencies as high as 90%. The control loop forces the CCFL PWM to modulate the average inductor current to maintain constant current in the lamp. The constant current value, and thus lamp intensity, is programmable. This drive technique provides a wide range of intensity control. A unique lamp-current programming block permits either grounded lamp or floating lamp configurations. Grounded lamp circuits directly sense one-half of average lamp current. Floating lamp circuits directly sense the Royer's primary-side converter current. Floating-lamp circuits provide symmetric differential drive to the lamp and reduce the parasitic loss from stray lampto-frame capacitance, extending illumination range. Block Diagram Operation The LT1786F is a fixed frequency, current mode switching regulator. A fixed frequency, current mode switcher controls switch duty cycle directly by switch current rather than by output voltage. Referring to the block diagram for the LT1786F, the switch turns ON at the start of each oscillator cycle. The switch turns OFF when switch current reaches a predetermined level. The control of output lamp current is obtained by using the output of a unique programming block to set current trip level. The current mode switching technique has several advantages. First, it provides excellent rejection of input voltage variations. Second, it reduces the 90 phase shift at mid-frequencies in the energy storage inductor. This simplifies closed-loop frequency compensation under widely varying input voltage or output load conditions. Finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under output overload or short-circuit conditions. The LT1786F incorporates a low dropout internal regulator that provides a 2.4V supply for most of the internal circuitry. This low dropout design allows input voltage to vary from 3V to 6.5V with little change in quiescent current. An active low shutdown pin typically reduces total supply current to 150A by shutting off the 2.4V regulator and locks out switching action for standby operation. The IC incorporates undervoltage lockout by sensing regulator dropout and locking out switching below about 2.5V. The regulator also provides thermal shutdown protection that locks out switching in the presence of excessive junction temperatures. A 200kHz oscillator is the basic clock for all internal timing. The oscillator turns on the output switch via its own logic and driver circuitry. Adaptive anti-sat circuitry detects the onset of saturation in the power switch and adjusts base drive current instantaneously to limit switch saturation. This minimizes driver dissipation and provides rapid turnoff of the switch. The CCFL power switch is guaranteed to provide a minimum of 1.25A in the LT1786F. The antisat circuitry provides a ratio of switch current to driver current of about 50:1. Digital Interface The LT1786F communicates with an SMBus host using the standard 2-wire SMBus interface. The Timing Diagram shows the signals on the SMBus. The two bus lines SDA and SCL must be high when the bus is not in use. External pull-up resistors or current sources are required at these lines. The LT1786F is a receive-only (slave) device. The master must apply the following Write Byte protocol to communicate with the LT1786F:
1 7 1 1 8 1 8 Data Byte 1 A 1 P S Slave Address WR A Command Byte A
12
U
W
U
U
S = Start Conditon, WR = Write Bit, A = Acknowledge Bit, P = Stop Condition
The master initiates communication with the LT1786F with a START condition (see SMBus Operating Sequence) and a 7-bit address followed by the write bit = 0. The LT1786F acknowledges and the master delivers the command byte. The LT1786F acknowledges and latches the active bits of the command byte into register A (see Block Diagram) at the falling edge of the acknowledge pulse. The master sends the data byte and the LT1786F acknowledges the data byte. The data byte is latched into register C at the falling edge of the final acknowledge pulse and the DAC current output assumes the new 6-bit data
LT1786F
APPLICATIONS INFORMATION
value (see Block Diagram). A STOP condition is optional. The command code and data byte are defined with the following format:
Command Code
7 6543210 SHDN X X X X X X X
Data Byte
7 6 5 4 3 2 1 0 X D5 D4 D3 D2 D1 D0 X
SHDN: 0 for normal operation, 1 for shutdown D5 to D0: DAC Data Byte Bits, D5 is the Most Significant Bit
START and STOP Conditions At the beginning of any SMBus communication, the master must transmit a START condition by switching SDA from high to low while SCL is high. When a master has finished communicating with a slave device, a STOP condition is issued by switching SDA from low to high while SCL is high. The SMBus is then free for communication with another SMBus device. Early STOP Conditions The LT1786F recongnizes a STOP condition at any point in the SMBus communication sequence. If the STOP occurs prematurely before the data byte is acknowledged in the Write Byte protocol, the DAC output current value is not updated; otherwise internal register C is updated with the new data and the DAC output current changes correspondingly. The Slave Address The LT1786F responds to one of two 7-bit addresses. The first five bits have been factory programmed to 01011. The last two address bits are programmed by the user by tying the ADR pin to VCC or GND (see functional table)
ADR GND VCC SMBus ADDRESS 0101101 0101100 DAC POWER-UP VALUE Zero Scale Midscale
U
W
U
U
6-Bit Current Output DAC The 6-bit current output DAC is guaranteed monotonic and is digitally adjustable in 63 equal steps. On power-up, if ADR connects to VCC, the 6-bit internal register C (see Block Diagram) resets to 100000B and the DAC output is set to midrange. On power-up, if ADR connects to ground, register C resets to 000000B and the DAC output is set to zero. For the LT1786F, the current source output (IOUT) can be biased from - 10V to (VCC - 1.3V). Full-scale current is trimmed to 2% at room temperature and 4% over the commercial temperature range. Shutdown Three methods may be employed to shut down the LT1786F (see Block Diagram). The LT1786F enters SMBus suspend mode if a logic low level is applied to the SMBSUS pin or a logic high level is applied to Bit 7 in the Command Byte of the SMBus communication sequence. In SMBus suspend mode, supply current typically drops to 40A and the last output current setting is internally retained. The DAC resumes this level upon its return to normal operation. Enabling an SMBus suspend condition also turns on an open-drain N-channel MOSFET which pulls the SHDN pin low. The N-channel device sinks up to 1.6mA at the SHDN pin and its logic low level is guaranteed to less than 0.4V. The LT1786F enters regulator shutdown mode if a logic low level is applied to the SHDN pin. In this mode, supply current typically drops to 150A, the switching regulator circuitry is shut down and the DAC is kept alive. The DAC output current setting is maintained. This feature can be used to program the DAC to a desired output current level (other than the preset zero-scale or midscale level defined by the selected SMBus address) before allowing the CCFL regulator to turn on.
13
LT1786F
APPLICATIONS INFORMATION
LT1786F SMBus Lookup Tables
SMBus Address Byte Table
ADR GND VCC DECIMAL 91 88 BINARY 0101101 0101100 HEX 5A 58 IOUT POWER-UP VALUE Zero Scale Midscale
Bit 0 (LSB) in the SMBus Address is the Write Bit = 0
SMBus Data Byte Table
DECIMAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BINARY 000000XX 000001XX 000010XX 000011XX 000100XX 000101XX 000110XX 000111XX 001000XX 001001XX 001010XX 001011XX 001100XX 001101XX 001110XX 001111XX 010000XX 010001XX 010010XX 010011XX 010100XX 010101XX 010110XX 010111XX 011000XX 011001XX 011010XX 011011XX 011100XX 011101XX 011110XX 011111XX HEX 00-03 04-07 08-0B 0C-0F 10-13 14-17 18-1B 1C-1F 20-23 24-27 28-2B 2C-2F 30-33 34-37 38-3B 3C-3F 40-43 44-47 48-4B 4C-4F 50-53 54-57 58-5B 5C-5F 60-63 64-67 68-6B 6C-6F 70-73 74-77 78-7B 7C-7F IOUT (A) 0.000 1.587 3.175 4.762 6.349 7.937 9.524 11.111 12.698 14.286 15.873 17.460 19.048 20.635 22.222 23.810 25.397 26.984 28.571 30.159 31.746 33.333 34.921 36.508 38.095 39.683 41.270 42.857 44.444 46.032 47.619 49.206 DECIMAL 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 BINARY 100000XX 100001XX 100010XX 100011XX 100100XX 100101XX 100110XX 100111XX 101000XX 101001XX 101010XX 101011XX 101100XX 101101XX 101110XX 101111XX 110000XX 110001XX 110010XX 110011XX 110100XX 110101XX 110110XX 110111XX 111000XX 111001XX 111010XX 111011XX 111100XX 111101XX 111110XX 111111XX HEX 80-83 84-87 88-8B 8C-8F 90-93 94-97 98-9B 9C-9F A0-A3 A4-A7 A8-AB AC-AF B0-B3 B4-B7 B8-BB BC-BF C0-C3 C4-C7 C8-CB CC-CF D0-D3 D4-D7 D8-DB DC-DF E0-E3 E4-E7 E8-EB EC-EF F0-F3 F4-F7 F8-FB FC-FF IOUT (A) 50.794 52.381 53.968 55.556 57.143 58.730 60.317 61.905 63.492 65.079 66.667 68.254 69.841 71.429 73.016 74.603 76.190 77.778 79.365 80.952 82.540 84.127 85.714 87.302 88.889 90.476 92.063 93.651 95.238 96.825 98.413 100.000
X = Don't Care, IOUT = Ideal Value
14
U
W
U
U
SMBus Command Byte Table
DECIMAL 0-127 128-255
X = Don't Care
BINARY 0XXXXXXX 1XXXXXXX
HEX 00-7F 80-FF
MODE Normal Shutdown
LT1786F
APPLICATIONS INFORMATION
Simplified Lamp Current Programming A programming block in the LT1786F controls lamp current, permitting either grounded lamp or floating lamp configurations. Grounded configurations control lamp current by directly controlling one-half of actual lamp current and converting it to a feedback signal to close a control loop. Floating configurations control lamp current by directly controlling the Royer's primary-side converter current and generating a feedback signal to close a control loop. Previous backlighting solutions have used a traditional error amplifier in the control loop to regulate lamp current. This approach converted an RMS current into a DC voltage for the input of the error amplifier. This approach used several time constants in order to provide stable loop frequency compensation. This compensation scheme meant that the loop had to be fairly slow and that output overshoot with start-up or overload conditions had to be carefully evaluated in terms of transformer stress and breakdown voltage requirements. The LT1786F eliminates the error amplifier concept entirely and replaces it with a lamp current programming block. This block provides an easy-to-use interface to program lamp current. The programmer circuit also reduces the number of time constants in the control loop by combining the error signal conversion scheme and frequency compensation into a single capacitor. The control loop thus exhibits the response of a single pole system, allows for faster loop transient response and virtually eliminates overshoot under start-up or overload conditions. Lamp current is programmed at the input of the programmer block, the ICCFL pin. This pin is the input of a shunt regulator and accepts a DC input current signal of 0A to 100A from the DAC. This input signal is converted to a 0A to 500A source current at the CCFL VC pin. The programmer circuit is simply a current-to-current converter with a gain of five. The ICCFL pin is sensitive to capacitive loading and will oscillate with capacitance greater than 10pF. For example, loading the ICCFL pin with a 1x or 10x scope probe causes oscillation and erratic CCFL regulator operation because of the probe's respective input capacitance. A current meter in series with the ICCFL pin will also produce oscillation due to its shunt capacitance. Use a decoupling resistor of several kilohms between the ICCFL pin and the IOUT pin if excessive trace stray capacitance exists. Normally, this resistor is not required. In some applications, the maximum programming current required at the ICCFL pin for a maximum lamp current will be less than the full-scale output current of the DAC, which is 100A. The system designer can either limit the maximum programming current through software built into the system, or use a current splitter which shunts a percentage of the fullscale current from the ICCFL pin. A splitter circuit is illustrated in Figure 1. A divider string is used from a reference voltage to set up a voltage level equal to the ICCFL summing voltage, or 465mV. The main current flowing in the divider string should be chosen to swamp out the effects of the shunted current into the divider string.
IOUT FULL-SCALE 100A I V1 V(ICCFL) 465mV VREF I1 R3 V(ICCFL) (1 - X)I R4 I = 100A 0> (1 - X)I R1 = (V1 - 0.465)/[(X)(100A)] R2 = (V1 - 0.465)/[(1 - X)(100A)] R3 = (VREF - 0.465)/I1 R4 = 0.465R3/[(1 - X)(100A)(R3) + (VREF - 0.465)] 1786 F01
U
W
U
U
R1 XI R2
Figure 1
Grounded Lamp Configuration In a grounded lamp configuration, the low voltage side of the lamp connects directly to the LT1786F DIO pin. This pin is the common connection between the cathode and anode of two internal diodes. In previous grounded lamp solutions, these diodes were discrete units and are now integrated onto the IC, saving cost and board space. Bidirectional lamp current flows in the DIO pin and thus, the diodes conduct alternately on half cycles. Lamp current is controlled by monitoring one-half of the average lamp current. The diode conducting on negative half cycles has one-tenth of its current diverted to the CCFL VC pin and nulls against the source current provided by the
15
LT1786F
APPLICATIONS INFORMATION
lamp current programmer circuit. The compensation capacitor on the CCFL VC pin provides stable loop compensation and an averaging function to the rectified sinusoidal lamp current. Therefore, input programming current relates to one-half of average lamp current. The transfer function between lamp current and input programming current must be empirically determined and is dependent on the particular lamp/display housing combination used. The lamp and display housing are a distributed loss structure due to parasitic lamp-to-frame capacitance. This means that the current flowing at the highvoltage side of the lamp is higher than what is flowing at the DIO pin side of the lamp. The input programming current is set to control lamp current at the high-voltage side of the lamp, even though the feedback signal is the lamp current at the bottom of the lamp. This ensures that the lamp is not overdriven which can degrade the lamp's operating lifetime. Therefore, the full scale current of the DAC does not necessarily correspond to the current required to set maximum lamp current. Floating Lamp Configuration In a floating lamp configuration, the lamp is fully floating with no galvanic connection to ground. This allows the transformer to provide symmetric differential drive to the lamp. Balanced drive eliminates the field imbalance associated with parasitic lamp-to-frame capacitance and reduces "thermometering" (uneven lamp intensity along the lamp length) at low lamp currents. Carefully evaluate display designs in relation to the physical layout of the lamp, its leads and the construction of the display housing. Parasitic capacitance from any high voltage point to DC or AC ground creates paths for unwanted current flow. This parasitic current flow degrades electrical efficiency and losses up to 25% have been observed in practice. As an example, at a Royer operating frequency of 60kHz, 1pF of stray capacitance represents an impedance of 2.65M. With an operating lamp voltage of 400V and an operating lamp current of 6mA, the parasitic current is 150A. This additional current must be supplied by the transformer secondary. Layout techniques that increase parasitic capacitance include long high voltage lamp leads, reflective metal foil around the lamp and displays supplied in metal enclosures. Losses for a good display are under 5%, whereas, losses for a bad display range from 5% to 25%. Lossy displays are the primary reason to use a floating lamp configuration. Providing symmetric, differential drive to the lamp reduces the total parasitic loss by one-half. Maintaining closed-loop control of lamp current in a floating lamp configuration necessitates deriving a feedback signal from the primary side of the Royer transformer. Previous solutions have used an external precision shunt and high-side sense amplifier configuration. This approach has been integrated onto the LT1786F for simplicity of design and ease of use. An internal 0.1 resistor monitors the Royer converter current and connects between the input terminals of a high-side sense amplifier. A 0 - 1 Amp Royer primary-side, center-tap current is translated to a 0A to 500A sink current at the CCFL VC pin to null against the source current provided by the lamp current programmer circuit. The compensation capacitor on the CCFL VC pin provides stable loop compensation and an averaging function to the error sink current. Therefore, input programming current is related to average Royer converter current. Floating lamp circuits operate similarly to grounded lamp circuits except for the derivation of the feedback signal. The transfer function between lamp current and input programming current must be empirically determined and is dependent upon a myriad of factors including lamp characteristics, display construction, transformer turns ratio and the tuning of the Royer oscillator. Once again, lamp current will be slightly higher at one end of the lamp and input programming current should be set for this higher level to ensure that the lamp is not overdriven. The internal 0.1 high-side sense resistor on the LT1786F is rated for a maximum DC current of 1A. This resistor can be damaged by extremely high surge currents at start-up. The Royer converter typically uses a few microfarads of bypass capacitance at the center tap of the transformer. This capacitor charges up when the system is first powered by the battery pack or an AC wall adapter. The amount of current delivered at start-up can be very large if the total impedance in this path is small and the voltage source has high current capability. Linear Technology recommends
16
U
W
U
U
LT1786F
APPLICATIONS INFORMATION
the use of an aluminum electrolytic for the transformer center-tap bypass capacitor with an ESR greater than or equal to 0.5. This lowers the peak surge currents to an acceptable level. In general, the wire and trace inductance in this path also help reduce the di/dt of the surge current. This issue only exists with floating lamp circuits as grounded lamp circuits do not make use of the high-side sense resistor. Input Capacitor Type Caution must be used in selecting the input capacitor type for switching regulators. Aluminum electrolytics are electrically rugged and the lowest cost, but are physically large to meet required ripple current ratings, and size constraints (especially height) may preclude their use. Ceramic capacitors are now available in larger values and their high ripple current and voltage rating make them ideal for input bypassing. Solid tantalum capacitors would be a good choice except for a history of occasional failure when subjected to large current surges during start-up. The input bypass capacitor of regulators can see these high surges when a battery or high capacitance source is connected. Some manufacturers have developed tantalum capacitor lines specially tested for surge capability (AVX TPS series for instance), but even these units may fail if the input voltage surge approaches the capacitor's maximum voltage rating. AVX recommends derating the capacitor voltage by 2:1 for high surge applications. Applications Support Linear Technology invests an enormous amount of time, resources and technical expertise in understanding, designing and evaluating backlight/LCD contrast solutions for system designers. The design of an efficient and compact LCD backlight system is a study of compromise in a transduced electronic system. Every aspect of the design is interrelated and any design change requires complete re-evaluation for all other critical design parameters. Linear Technology has engineered one of the most complete test and evaluation setups for backlight designs and understands the issues and tradeoffs in achieving a compact, efficient and economical customer solution. Linear Technology welcomes the opportunity to discuss, design, evaluate and optimize any backlight/LCD contrast system with a customer. For further information on backlight/LCD contrast designs, consult the References. References 1. Williams, Jim. August 1992. Illumination Circuitry for Liquid Crystal Displays. Linear Technology Corporation, Application Note 49. 2. Williams, Jim. August 1993. Techniques for 92% Efficient LCD Illumination. Linear Technology Corporation, Application Note 55. 3. Bonte, Anthony. March 1995. LT1182 Floating CCFL with Dual Polarity Contrast. Linear Technology Corporation, Design Note 99. 4. Williams, Jim. April 1995. A Precision Wideband Current Probe for LCD Backlight Measurement. Linear Technology Corporation, Design Note 101. 5. LT1182/LT1183/LT1184/LT1184F Data Sheet. CCFL/ LCD Contrast Switching Regulators. April 1995. Linear Technology Corporation. 6. Williams, Jim. November 1995. A Fourth Generation of LCD Backlight Technology. Linear Technology Corporation, Application Note 65.
U
W
UU
17
LT1786F
TYPICAL APPLICATION
Dual Transformer CCFL Power Supply Space constraints may dictate utilization of two small transformers instead of a single, larger unit. Although this approach is somewhat more expensive, it can solve space problems and offers other attractive advantages. Figure 2's approach is essentially a "grounded lamp" LT1786Fbased circuit. The transistors drive two transformer primaries in parallel. The transformer secondaries, stacked in series, provide the output. The relatively small transformers, each supplying half the load power, may be located directly at the lamp terminals. Aside from the obvious space advantage (particularly height), this arrangement minimizes parasitic wiring losses by eliminating high voltage lead length. Additionally, although the lamp receives differential drive, with its attendant low parasitic losses, the feedback signal is ground referred. Thus, the stacked secondaries afford floating lamp operating efficiency with grounded mode current certainty and line regulation. L1 is directly driven, with winding 4-5 furnishing feedback in the normal fashion. L3, "slaved" to L1's and L3's interconnects must be laid out for low inductance to maintain waveform purity. The traces should be as wide as possible (e.g., 1/8") and overlaid to cancel inductive effects.
27pF LAMP 10 6 L1 3 2 1 4 5 WIDE TRACE SEE TEXT AND NOTES WIDE TRACE 0.1F* 3 2 1 2.2F 2.2F 1000pF 220k 0.1F* 4 NC 5 NC 6 10 L3
100k Q1-Q2 ZDT1048 750 +VBAT
1 2 3 4 1F 5 6 7 8
PGND ICCFL DIO VC AGND SHDN SMBSUS ADR
14 BAT LT1786F 13 ROYER VIN IOUT SCL SDA 12 11 10 9 TO SMBus HOST L1, L3 = COILTRONICS CTX110605 OVERLAY INDICATED TRACES BETWEEN L1 AND L3 L2 = COILTRONICS CTX100-4 * = WIMA MKI OR MKP-20 = PANASONIC ECH-U COILTRONICS (561) 241-7876
1786 F02
SHUTDOWN
Figure 2. Dual Transformers Save Space and Minimize parasitic Losses While Maintaining Current Accuracy and Line Regulation. Trade-Off Is Increased Cost
18
U
+
+
BAT54 16 15
L2 MBRS130L
VSW BULB
+
2.2F 16V
VIN 5V
LT1786F
PACKAGE DESCRIPTION
S Package 16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0 - 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted.
0.386 - 0.394* (9.804 - 10.008) 16 15 14 13 12 11 10 9
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
5
6
7
8
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
S16 0695
19
LT1786F
TYPICAL APPLICATION
90% Efficient Grounded CCFL with 2-Wire SMBus Control of Lamp Current
1 2 C7 1F 3
CCFL PGND ICCFL DIO
LT1786F 13 4 CCFL VC ROYER 5 AGND SHDN SMBSUS ADR VCC IOUT SCL SDA 12 11 10 9 TO SMBus HOST
SHUTDOWN
6 7 8
RELATED PARTS
PART NUMBER LT1172 LT1173 LT1182 LT1183 LT1184 LT1184F LT1186F LT1316 LT1372 DESCRIPTION Current Mode Switching Regulator for CCFL or LCD Contrast Control Micropower DC/DC Converter for LCD Contrast Control Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control Current Mode Switching Regulator for CCFL Control Current Mode Switching Regulator for CCFL Control DAC Programmable Current Mode Switching Regulator for CCFL Control Micropower DC/DC Converter for LCD Contrast Control Current Mode Switching Regulator for CCFL or LCD Contrast Contol COMMENTS 1.25A, 100kHz 1A, 24kHz, Hysteretic 1.25A, 0.625A, 200kHz 1.25A, 0.625A, 200kHz 1.25A, 200kHz 1.25A, 200kHz 1.25A, 200kHz, SPI or Pulse Mode Programmable Peak Current Limit 1.5A, 500kHz
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
LAMP 10 6
C2 27pF 3kV L1
3 C5 1000pF R2 221k 1% R3 100k 1% Q2 16 15 14
2
1 C3 2.2F 35V
4
5
+
BAT 8V TO 28V
C1 0.068F
R1 750 1%
D1 BAT85
Q1
CCFL VSW BULB BAT
L2 100H
D1 1N5818
1786F TA03
+
3V < VCC < 6.5V C4 2.2F
C1 MUST BE A LOW LOSS CAPACITOR C1 = WIMA MKI OR MKP-20 PANASONIC ECH-U L1 = COILTRONICS CTX210605 L2 = COILTRONICS CTX100-4 (DO NOT SUBSTITUTE COMPONENTS COILTRONICS (561) 241-7876) Q1, Q2 = ZETEX ZTX849 OR ROHM 25C5001
1786f LT/TP 0898 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

▲Up To Search▲

Price & Availability of LT1786F

	To Download LT1786F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .